1. Field of the Invention
The present invention relates to error correction systems, and more particularly, to error correction systems that use a combined encoder/syndrome generator to generate both check symbols and error syndromes.
2. Description of the Related Art
A combined encoder/syndrome generator is an error correction circuit that can generate both check symbols and error syndromes. The combined error/syndrome generator generates check symbols during an encoding process. The check symbols are appended to a bit stream.
The combined encoder/syndrome generator generates error syndromes during a decoding process. The error syndromes are transmitted to a decoder, which uses the error syndromes to compute error locations and error values. The error locations and error values are used to correct errors in the bit stream. A controller selects between the encoding and decoding operations of the combined encoder/syndrome generating circuit using a control signal.
A combined encoder/syndrome generator circuit has multiple stages that are coupled together in series. Each stage of the combined encoder/syndrome generator circuit typically includes one multiplier and one or two adders. One input for each stage of the circuit (except the first stage) is an output from the previous stage. As a result, the delay of the combined encoder/syndrome generator circuit increases as the number of stages in the circuit is increased. The delay of a combined encoder/syndrome generator circuit having a large number of stages can be significant.
Therefore, it would be desirable to provide a combined encoder/syndrome generator that has a reduced delay relative to many prior art circuits.